Self-aligned field effect transistors (FETS) are known in the art. During the formation of transistors of this nature, ion implantation has been used to form the heavily doped source and drain regions of the transistor so that the edges of the source and drain regions line up with the edges of the gate electrode. This doping of the source and drain regions is of course necessary since these regions are unmodulated by the gate electrode. Since there is no overlap of the source and drain regions with the gate electrode, the parasitic capacitance of the transistor is greatly reduced as compared to conventional transistors having gate electrodes and source and drain regions that overlap.
Parasitic capacitance affects the switching speed of a transistor. Therefore, in environments requiring high speed switching, such as in driver circuits for active matrix liquid crystal displays (AMLCDs), it is desired to minimize the parasitic capacitance of transistors to increase their switching speed. Although ion implantation methodology has allowed self-aligned transistors which reduce parasitic capacitance to be fabricated, ion implantation is a high energy process. Accordingly, alternative methods of doping semiconductor material and fabricating self-aligned transistors which reduce energy requirements are desired.
Therefore, it is an object of the present invention to provide a novel method of doping compound semiconductor material and a novel method of forming a self-aligned thin film transistor.